1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a memory device.
2. Description of the Related Art
For various non-volatile memories, electrically erasable programmable read-only memories (EEPROMs) can read, write, program and erase memory cells for multiple times and still maintain the stored data even when the power is off. Accordingly, EEPROMs have been widely applied in apparatus such as personal computers and electronic devices.
EEPROM is a non-volatile memory which has advantages such as small cell size, a high read/write speed and low power consumption. In addition, the data erasing in an EEPROM is performed by a block-by-block method. Therefore, EEPROM has a desired operational speed.
EEPROM comprises memory cells in the cell area and logic devices in the peripheral circuit. The memory cells and the logic devices are separated by shallow trench isolation (STI) structures. Moreover, since the operational voltages required for the memory cells and the logic devices are different the gate dielectric layers for the memory cells and the logic devices should be fabricated in separate processes.
FIGS. 1A–1C are cross sectional views showing a progression of a conventional method of fabricating EEPROM.
Referring to FIG. 1A, the substrate 100 is provided, which comprises the memory cell area 102 and the peripheral circuit area 104. The patterned tunneling layer 106, the floating gate 108 and the mask layer 110 are formed over the substrate 100. The mask layer 110 serves as a self-align mask for etching the substrate 100 so as to form the trenches 112 in the substrate 100 of the memory cell area 102 and the trenches 114 in the substrate 100 of the peripheral circuit 104.
Referring to FIG. 1B, the liner 116 is formed on the surfaces of the trenches 112 and 114, and sidewalls of the floating gate 108 and the tunneling layer 106. The isolation layer 118 is then filled in the trenches 112 and 114. The mask layer 110 and a portion of the isolation layer 118 are removed so as to form the isolation structure 120 in the memory cell area 102, and the isolation structure 122 in the peripheral circuit area 104.
Referring to FIG. 1C, the inter-gate dielectric layer 124 is formed over the surface of the floating gate 108 in the memory cell area 102. Then, the tunneling layer 106 and the floating gate 108 in the peripheral circuit area 104 are removed. The removing can be performed, for example, by a wet-etch process. Next, the gate dielectric layer 128 is formed over the substrate 100 in the peripheral circuit area 104. The control gate 130 is formed over the inter-gate dielectric layer 124 in the memory cell area 102. The gate layer 132 is formed over the gate dielectric layer 128 in the peripheral circuit area 104.
In the conventional process, the device isolation area, i.e. the area for the to-be-formed isolation structure, is defined by using the self-align mask so as to precisely control the critical dimension (CD) of the devices in the memory cell area 102. The logic devices in the peripheral circuit area 104, however, requires an operating voltage which is different from that of the memory cells in the memory cell area 102. Accordingly, the formed tunneling layer 106 cannot serve as a gate dielectric layer 128 for the logic devices and so the gate dielectric layer 128 should be formed in an additional process. Still, while forming the gate dielectric layer 128, the floating gate 108 and the tunneling layer 106 are first removed in an isotropic wet-etch process. As a result, the neighboring isolation structure 122 can be damaged during the etch process, forming an isolation structure with a hump shape 126 as shown. The isolation structure with the hump shape 126 will deteriorate electrical isolation of the isolation structure 122 in the peripheral circuit area 104, which will result in leakage currents. Moreover, during the subsequent process of forming the gate layer 132, the gate material may be filled in the notches of the isolation structure 122.